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Cypress Semiconductor /psoc63 /SRSS /CLK_PILO_CONFIG

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Interpret as CLK_PILO_CONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PILO_FFREQ0 (PILO_CLK_EN)PILO_CLK_EN 0 (PILO_RESET_N)PILO_RESET_N 0 (PILO_EN)PILO_EN

Description

Precision ILO Configuration Register

Fields

PILO_FFREQ

Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz.
PILO_CLK_EN

Enable the PILO clock output. See PILO_EN field for required sequencing.
PILO_RESET_N

Reset the PILO. See PILO_EN field for required sequencing.
PILO_EN

Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data